Minsoo Rhu
Associate Professor (Tenured)
KAIST, School of Electrical Engineering
Email: minsoo DOT rhu AT gmail DOT com
Tel: +82-42-350-7447
Office: N1 #809
Embedded Files
(Student recruiting) I am actively seeking self-motivated, resourceful, and dedicated students who are interested in building hardware/software systems for machine learning. Our group currently has multiple openings to hire graduate students (as well as undergraduate research interns). If you're interested in joining my research group, please apply through our school's graduate admission system, indicating you're interested in working with me. Please also shoot me a *short* email including your transcript and CV, briefly introducing yourself and explaining what you'd like to achieve through your graduate school experience.
About Me
About Me
I'm a Tenured Associate Professor at the School of Electrical Engineering, jointly affiliated with Department of Semiconductor System Engineering, Graduate School of Artificial Intelligence (AI), and Graduate School of AI Semiconductor at KAIST.
I am was a Senior Research Scientist working at the architecture research group at NVIDIA. I had an opportunity to work on a number of exciting projects at NVIDIA that span several areas in computing, which include ASIC designs, computer system architecture, runtime systems, and application & workload characterization with an emphasis on deep neural networks (DNNs). Initially at NVIDIA, I worked on developing microarchitectural support for high-performance GPU cache replacement policies. More recently, I have been working in the domain of deep learning, trying to come up with neat architectural enhancements to the GPU hardware/software stack so that NVIDIA maintains its leadership in the areas of machine learning. For instance, I led the research and development of the virtualized DNN runtime system, a high-performance GPU memory virtualization solution for DNN training. I was also the technical lead on the architecture design, implementation, and evaluation of the sparse CNN accelerator, an ASIC developed by NVIDIA Research aiming towards achieving high energy-efficiency for DNN inference.
In the past, I earned my Ph.D. degree from the University of Texas at Austin in 2014, under the guidance of professor Mattan Erez. I received my M.S. and B.E. degree from KAIST (Korea Advanced Institute of Science and Technology) and Sogang University, in 2009 and 2007, respectively.
Education
Education
The University of Texas at Austin, Austin, TX, USA [Sep. 2010 ~ May 2014]
Ph.D. in Computer Engineering
Dissertation : Performance-Efficient Mechanisms for Managing Irregularity in Throughput Processors
Advisor : Mattan Erez
KAIST (Korea Advanced Institute of Science and Technology), Daejeon, Korea [Feb. 2008 ~ Aug. 2009]
M.S. in Electrical Engineering
Dissertation : Analysis and Architecture Design of Binary Arithmetic Coder for JPEG2000
Advisor : In-Cheol Park
Sogang University, Seoul, Korea [Mar. 2001 ~ Jun. 2003, Mar. 2006 ~ Aug. 2007]
B.S. in Electronic Engineering
Summa Cum Laude
Valedictorian (Graduated 1st in the class of 2007)
Work Experience
Work Experience
KAIST (Korea Advanced Institute of Science and Technology), Daejeon, South Korea
Associate Professor (with Tenure) [September 2024 ~ Present]
Associate Professor (without Tenure) [September 2020 ~ September 2024]
Assistant Professor [July 2018 ~ August 2020]
Meta AI, Boston MA
Research Scientist [August 2022 ~ August 2023]
POSTECH (Pohang University of Science and Technology), Pohang, South Korea
Assistant Professor [June 2017 ~ July 2018]
NVIDIA Research, Austin TX
Senior Research Scientist [Feb 2017 ~ May 2017]
Research Scientist [May 2014 ~ Jan 2017]
Manager: Steve Keckler
Project:
NVIDIA Research, Austin, TX
Research Internship [May 2013 ~ Nov. 2013]
Manager: Steve Keckler
Mentor: Daniel Johnson, Mike O'Connor
Project:
Priority-based cache allocation for throughput processors ([US patent])
Samsung Advanced Institute of Technology, Giheung, South Korea
Research Internship [Jun. 2009 ~ Aug. 2009]
Academic Service
Academic Service
Program Committee Chair
IEEE/ACM International Symposium on Microarchitecture (MICRO): 2025
Program Committee
IEEE/ACM International Symposium on Microarchitecture (MICRO): 2016, 2017, 2018, 2019, 2020, 2021, 2022, 2023, 2024
IEEE/ACM International Symposium on Computer Architecture (ISCA): 2020, 2024, 2025
IEEE International Symposium on High-Performance Computer Architecture (HPCA): 2019, 2021, 2023, 2024, 2025
ACM/ESDA/IEEE Design Automation Conference (DAC): 2018, 2019, 2020, 2021
IEEE International Conference for High Performance Computing, Networking, Storage, and Analysis (SC): 2016, 2019
ACM European Conference on Computer Systems (EuroSys): 2024
International Conference on Machine Learning and Systems (MLSys): 2022
ACM International Conference on Supercomputing (ICS): 2021
IEEE International Symposium on Workload Characterization (IISWC): 2018, 2022
IEEE International Parallel and Distributed Processing Symposium (IPDPS): 2020
IEEE Cluster conference (CLUSTER): 2019
IEEE International Conference on Computer Design (ICCD): 2016, 2021
External Program Committee
Organization Committee
Associate Editor
IEEE Transactions on Computers (TC)
Journal Reviewer
Google Sites
Report abuse